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i PEM 2.4Gb 2.4Gb SDRAM-DDR Austin Semiconductor, Inc. AS4DDR32M72PBG1 32Mx72 DDR SDRAM iNTEGRATED Plastic Encapsulated Microcircuit
FEATURES
DDR SDRAM Data Rate = 200, 250, 266, 333Mbps Package: * 208 Plastic Ball Grid Array (PBGA), 16 x 23mm-1.0mm pitch 2.5V 0.2V core power supply 2.5V I/O (SSTL_2 compatible) Differential clock inputs (CLK and CLK#) Commands entered on each positive CLK edge Internal pipelined double-data-rate (DDR) architecture; two data accesses per clock cycle Programmable Burst length: 2,4 or 8 Bidirectional data strobe (DQS) transmitted/received with data, i.e., source-synchronous data capture (one per byte) DQS edge-aligned with data for READs; center-aligned with data for WRITEs DLL to align DQ and DQS transitions with CLK Four internal banks for concurrent operation Two data mask (DM) pins for masking write data Programmable IOL/IOH option Auto precharge option Auto Refresh and Self Refresh Modes Industrial, Enhanced and Military Temperature Ranges Organized as 32M x 72/80 Weight: AS4DDR32M72PBG * This product and or it's specifications is subject to change without notice.
BENEFITS
40 - 70% SPACE SAVINGS Reduced part count Reduced I/O count * 34% I/O Reduction Reduced trace lengths for lower parasitic capacitance Suitable for hi-reliability applications Laminate interposer for optimum TCE match PIN/Function compatible to White W3E32M72S-xSBx
Configuration Addressing Parameter Configuration Refresh Count Row Address Bank Address Column Address 32 Meg x 72 8 Meg x 16 x 4 Banks 8K 8K (A0 A12) 4 (BA0 BA1) 1K (A0 A9)
FUNCTIONAL BLOCK DIAGRAM
CLK0 CLK0\ CKE0 CS0 WE0\ RAS0\ CAS0\ DQML0 DQMH 0 DQSL0 DQSH 0 VRef VCC VCCQ VSS Ax,BA0-1 CLK2 CLK2\ CKE2 CS2 WE2\ RAS2\ CAS2\ DQML2 DQMH 2 DQSL2 DQSH 2 SD R AM DDR x16
2.5V Cor e 2.5V I/O
SD R AM DDR x16
2.5V Core 2.5V I/O
CLK1 CLK1\ CKE1 DQ0-15 CS0 WE1\ RAS1\ CAS1\ DQML1 DQMH 1 DQSL1 DQSH1
CLK4 CLK4\ SD R AM DDR x16
2.5V Core 2.5V I/O
CKE4 CS4 DQ16-31 WE4\ RAS4\ CAS4\ DQML4 DQMH 4 DQSL4 DQSH 4
SD R AM DDR x16
2.5V Core 2.5V I/O
DQ64-79
CLK3 CLK3\ CKE3 DQ32-47 CS3 WE3\ RAS3\ CAS3\ DQML3 DQMH 3 DQSL3 DQSH3 SD R AM DDR x16
2.5V Core 2.5V I/O
DQ48-63
AS4DDR32M72PBG1 Rev. 0.1 06/09
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i PEM 2.4Gb 2.4Gb SDRAM-DDR Austin Semiconductor, Inc. AS4DDR32M72PBG1
SDRAM-DDR Pinout Top View
Rev. A, 12/07, 208BGA-1.00MM PITCH - X72
1 A B C VCCQ VSS 2 VCC VSS CK0\ 3 VSS CS2\ CK2\ 4 VCCQ CS0\ CK0 5 VCCQ CKE2 CK2 DQ8 DQ43 DQ14 DQ48 DQ67 VCC VSS VCCQ DQ68 DQ48 DQ17 DQ51 DQ20 6 VSS CKE0 7 VCCQ CAS2\ 8 VCCQ RAS0\ CAS0\ DQ39 DQ36 DQ34 DQ0 DQ73 A7 VCCQ A6 9 VSS RAS2\ WE0\ DQ7 DQ4 DQ2 DQ77 DQ74 A9 A4 A8 CK4\ DQ62 DQ29 DQ26 10 VCC VSS WE2\ 11 VSS A
VCCQ B VSS C
DQML0 DQML2 DQ40 DQ12 DQ33 VSS VCC VSS VREF VSS VCC VSS DQ49 DQ60 DQ56 DQ5 DQ3 DQ1 DQ32 DQ72 VCCQ VSS VCC
D DQMH2 DQMH0 DQSH2 DQSH0 E F G H J K L M N P R T U V W DQ41 DQ44 DQ64 DNU VCCQ VSS VCC DQ71 WE4\ DQ22 DQ23 DQ9 DQ11 DQ65 DQ66 A12 A10 A2 DQ70 CAS4\ DQ52 DQ54 DQ10 DQ13 DQ15 DQ69 BA1 A3 BA0 DQ42 DQ45 DQ47 DNU A0 VCCQ A1
DQSL2 DQSL0 D DQ38 DQ37 DQ79 DQ75 DNU A11 A5 CK4 CKE4 DQ59 DQ57 DQ6 E
DQ36 F DQ78 G DQ76 H VCC VSS J K
VCCQ L DNU CS4\ M N
DQSL4 DQML4 RAS4\ DQ18 DQ21 DQ55 WE3\ CAS1\ VSS 3 DQ16 DQ50 DQ19 DQ53 WE1\ RAS3\ VCCQ 4
DQSH4 DQMH4 DQ63 DQ30 DQ28 DQ24 CK1\ CKE3 VCCQ 7 DQ31 DQ61 DQ58
DQ27 p DQ25 R
DQSL1 DQSL3 VSS VCCQ VSS 1 CAS3\ VSS VCC 2
DQMH3 DQMH1 DQSH1 DQSH3 T CK3\ CS1\ VCCQ 8 CK1 CS3\ VSS 9 CK3 VSS VCC 10 VSS U
DQML3 DQML1 RAS1\ VCCQ 5 CKE1 VSS 6
VCCQ V VSS 11 W
Ground CNTRL Data I/O
Array Power I/O Power Level REF.
UNPOPULATED NC
Address DNU
AS4DDR32M72PBG1 Rev. 0.1 06/09
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i PEM 2.4Gb 2.4Gb SDRAM-DDR Austin Semiconductor, Inc. AS4DDR32M72PBG1
PIN DEFINITIONS / FUNCTIONAL DESCRIPTION
BGA Location B5,B6,N10,V6,V7 C4,C5,M10,U9,U10 C2,C3,M9,U7,U8 B3,B4,N11,V8,V9 B7,C8,N2,U2,V3 B8,B9,N4,V4,V5 C9,C10,N1U3,U4 C6,C7M4,U5,U6 D1,D2,M8,T8,T9 D10,D11M3,T1,T2 D3,D4M7,T10,T11 J4,L4,L2,K3,K9,L10, L8,J8,L9,J9,K2,K10, J2 L3, J3 H1,H3,J10,M11 D5,D6,D7,D8,D9,E1,E2, E3,E4,E5,E6,E7,E8,E9, E10,E11,F1,F2,F3,F4, F5,F6,F7,F8,F9,F10, G1,G2,G3,G4,G5,G7, G8,G9,G10,G11,H2,H3, H5,H7,H8,H9,H10,H11, M1,M2,M5,N4,N5,N7,N8, N9,P1,P2,P3,P4,P5,P6, P7,P8,P9,P10,P11,R1, R2,R3,R4,R5,R6,R7,R8, R9,R10,R11,T3,T4,T5, T6,T7, T6 T7 K6 A2,A10,H6,J5,J11,L1, L7,M6,W2,W10 A4,A5,A7,A8,B1,B2,J1, J7,K4,K8,L5,L11,V1, V11,W4,W5,W7,W8 A3,A6,A9,A11,B2,B10, C1,C11,G6,J6,K1,K5, K7,K11,L6,N6,U1,U11, V2,V10,W1,W3,W6,W9, W11 Symbol CKEx CKx CKx\ CSx\ CASx\ RASx\ WEx\ DQMLx DQMHx DQSLx DQSHx Ax BAx DNU Type Description Clock Enable, enabler of all on silicon clock circuitry Clock input (active HIGH) part of a differential pair (1 pair per x16 bits) Clock input (active LOW) part of a differential pair (1pair per x16 bits) Chip Selects, one per x16 bits (active LOW) Column Address Select (1 per x16 bits) Row Address Select (1 per x16 bits) WRITE enable input (active LOW, 1 per x16 bits)
CNTL Input
Array Address input providing ROW addresses for ACTIVE commands and ADDR Input the COLUMN address and AUTO PRECHARGE bit (A10) for READ/WRITE commands Input Bank Address select input Future Use
DQx
Input/Output Data, bi-directional Input/Output pins
Vref VCC VCCQ
Supply Supply Supply
SSTL-25 Voltage Reference Core Power Supply IO Power Supply
VSS
Supply
Ground Return
UNPOPULATED
Unpopulated ball matrix location (location registration aid)
AS4DDR32M72PBG1 Rev. 0.1 06/09
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
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i PEM 2.4Gb 2.4Gb SDRAM-DDR Austin Semiconductor, Inc. AS4DDR32M72PBG1
GENERAL DESCRIPTION
The 2.4Gb DDR SDRAM MCM, is a high-speed CMOS, dynamic random-access, memory using 5 chips containing 536,870,912 bits. Each chip is internally configured as a quad-bank DRAM. Each of the chip's 134,217,728-bit banks is organized as 8,192 rows by 1024 columns by 32 bits. The 256MB(2.4Gb) DDR SDRAM MCM uses a DDR architecture to achieve high-speed operation. The double data rate architecture is essentially a 2n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the 256MB DDR SDRAM effectively consists of a single 2nbit wide, one-clock-cycle data tansfer at the internal DRAM core and two corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O pins. A bidirectional data strobe (DQS) is transmitted externally, along with data, for use in data capture at the receiver. DQS is a strobe transmitted by the DDR SDRAM during READs and by the memory contoller during WRITEs. DQS is edgealigned with data for READs and center-aligned with data for WRITEs. Each chip has two data strobes, one for the lower byte and one for the upper byte. The 256MB DDR SDRAM operates from a differential clock (CLK and CLK#); the crossing of CLK going HIGH and CLK# going LOW will be referred to as the positive edge of CLK. Commands (address and control signals) are registered at every positive edge of CLK. Input data is registered on both edges of DQS, and output data is referenced to both edges of DQS, as well as to both edges of CLK. Read and write accesses to the DDR SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed. The address bits registered coincident with the READ or WRITE command are used to select the bank and the starting column location for the burst access. The DDR SDRAM provides for programmable READ or WRITE burst lengths of 2, 4, or 8 locations. An auto precharge function may be enabled to provide a selftimed row precharge that is initiated at the end of the burst access. The pipelined, multibank architecture of DDR SDRAMs allows for concurrent operation, thereby providing high effective bandwidth by hiding row precharge and activation time. An auto refresh mode is provided, along with a powersaving power-down mode.
FUNCTIONAL DESCRIPTION
Read and write accesses to the DDR SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA0 and BA1 select the bank, A0-12 select the row). The address bits registered coincident with the READ or WRITE command are used to select the starting column location for the burst access. Prior to normal operation, the SDRAM must be initialized. The following sections provide detailed information covering device initialization, register defi nition, command descriptions and device operation.
INITIALIZATION
DDR SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation. Power must first be applied to VCC and VCCQ simultaneously, and then to VREF (and to the system VTT). VTT must be applied after VCCQ to avoid device latch-up, which may cause permanent damage to the device. VREF can be applied any time after VCCQ but is expected to be nominally coincident with VTT. Except for CKE, inputs are not recognized as valid until after VREF is applied. CKE is an SSTL_2 input but will detect an LVCMOS LOW level after VCC is applied. Maintaining an LVCMOS LOW level on CKE during powerup is required to ensure that the DQ and DQS outputs will be in the High-Z state, where they will remain until driven in normal operation (by a read access). After all power supply and reference voltages are stable, and the clock is stable, the DDR SDRAM requires a 200s delay prior to applying an executable command. Once the 200s delay has been satisfied, a DESELECT or NOP command should be applied, and CKE should be brought HIGH. Following the NOP command, a PRECHARGE ALL command should be applied. Next a LOAD MODE REGISTER command should be issued for the extended mode register (BA1 LOW and BA0 HIGH) to enable the DLL, followed by another LOAD MODE REGISTER command to the mode register (BA0/ BA1 both LOW) to reset the DLL and to program the operating parameters. Two-hundred clock cycles are required between the DLL reset and any READ command. A PRECHARGE ALL command should then be applied, placing the device in the all banks idle state. Once in the idle state, two AUTO REFRESH cycles must be performed (tRFC must be satisfi ed.) Additionally, a LOAD MODE REGISTER command for the mode register with the reset DLL bit deactivated (i.e., to program operating parameters without resetting the DLL) is required. Following these requirements, the DDR SDRAM is ready for normal operation.
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS4DDR32M72PBG1 Rev. 0.1 06/09
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REGISTER DEFINITION MODE REGISTER
The Mode Register is used to define the specific mode of operation of the DDR SDRAM. This definition includes the selection of a burst length, a burst type, a CAS latency, and an operating mode, as shown in Figure 3. The Mode Register is programmed via the MODE REGISTER SET command (with BA0 = 0 and BA1 = 0) and will retain the stored information until it is programmed again or the device loses power. (Except for bit A8 which is self clearing). Reprogramming the mode register will not alter the contents of the memory, provided it is performed correctly. The Mode Register must be loaded (reloaded) when all banks are idle and no bursts are in progress, and the controller must wait the specified time before initiating the subsequent operation. Violating either of these requirements will result in unspecified operation. Mode register bits A0-A2 specify the burst length, A3 specifies the type of burst (sequential or interleaved), A4-A6 specify the CAS latency, and A7-A12 specify the operating mode.
TABLE 1 - BURST DEFINITION
Burst Length 2 Starting Column Address A0 0 1 A1 A0 0 0 0 1 1 0 1 1 A2 A1 A0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Order of Accesses Within a Burst Type = Sequential Type = Interleaved 0-1 1-0 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 0-1 1-0 0-1-2-3 1-0-3-2 2-3-0-1 3-2-1-0 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4 4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0
4
8
BURST LENGTH
Read and write accesses to the DDR SDRAM are burst oriented, with the burst length being programmable, as shown in Figure 3. The burst length determines the maximum number of column locations that can be accessed for a given READ or WRITE command. Burst lengths of 2, 4 or 8 locations are available for both the sequential and the interleaved burst types. Reserved states should not be used, as unknown operation or incompatibility with future versions may result. When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is reached. The block is uniquely selected by A1-Ai when the burst length is set to two; by A2-Ai when the burst length is set to four (where Ai is the most significant column address for a given configuration); and by A3-Ai when the burst length is set to eight. The remaining (least significant) address bit(s) is (are) used to select the starting location within the block. The programmed burst length applies to both READ and WRITE bursts.
NOTES: 1. For a burst length of two, A1-Ai select two-data-element block; A0 selects the starting column within the block. 2. For a burst length of four, A2-Ai select four-data-element block; A0-1 select the starting column within the block. 3. For a burst length of eight, A3-Ai select eight-data-element block; A0-2 select the starting column within the block. 4. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block.
READ LATENCY
The READ latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first bit of output data. The latency can be set to 2 or 2.5 clocks. If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available by clock edge n+m. Table 2 below indicates the operating frequencies at which each CAS latency setting can be used. Reserved states should not be used as unknown operation or incompatibility with future versions may result.
TABLE 2 - CAS LATENCY
ALLOWABLE OPERATING FREQUENCY (MHz) CAS CAS LATENCY=2 LATENCY=2.5 75 100 100 125 100 133 100 166
BURST TYPE
Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit M3. The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in Table 1.
SPEED -10 -8 -75 -6
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OPERATING MODE
The normal operating mode is selected by issuing a MODE REGISTER SET command with bits A7-A12 each set to zero, and bits A0-A6 set to the desired values. A DLL reset is initiated by issuing a MODE REGISTER SET command with bits A7 and A9-A12 each set to zero, bit A8 set to one, and bits A0-A6 set to the desired values. Although not required, JEDEC specifications recommend when a LOAD MODE REGISTER command is issued to reset the DLL, it should always be followed by a LOAD MODE REGISTER command to select normal operating mode. All other combinations of values for A7-A12 are reserved for future use and/or test modes. Test modes and reserved states should not be used because unknown operation or incompatibility with future versions may result.
FIGURE 1 - MODE BURST DEFINITION
BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Address Bus
Mode Register (Mx)
0*
0*
Operating Mode
CAS Latency
BT
Burst Length
* M14 and M13 (BA0 and BA1 must be "0, 0" to select the base mode register (vs. the extended mode register).
Burst Length M2 M1 M0 0 0 0 0 1 1 1 1 00 01 10 11 00 01 10 11 M3 = 0 Reserved 2 4 8 Reserved Reserved Reserved Reserved M3 = 1 Reserved 2 4 8 Reserved Reserved Reserved Reserved
EXTENDED MODE REGISTER
The extended mode register controls functions beyond those controlled by the mode register; these additional functions are DLL enable/disable, output drive strength, and QFC#. These functions are controlled via the bits shown in Figure 3. The extended mode register is programmed via the LOAD MODE REGISTER command to the mode register (with BA0 = 1 and BA1 = 0) and will retain the stored information until it is programmed again or the device loses power. The enabling of the DLL should always be followed by a LOAD MODE REGISTER command to the mode register (BA0/BA1 both LOW) to reset the DLL. The extended mode register must be loaded when all banks are idle and no bursts are in progress, and the controller must wait the specified time before initiating any subsequent operation. Violating either of these requirements could result in unspecified operation.
M12 0 0 M11 0 0 M10 0 0 M9 0 0 M8 0 1 M7 0 0 M3 0 1 Burst Type Sequential Interleaved
M6 M5 M4 0 0 0 0 1 1 1 1 00 01 10 11 00 01 10 11
CAS Latency Reserved Reserved 2 Reserved Reserved Reserved 2.5 Reserved
M6-M0 Valid Valid -
Operating Mode Normal Operation Normal Operation/Reset DLL All other states reserved
AS4DDR32M72PBG1 Rev. 0.1 06/09
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FIGURE 2 - CAS LATENCY
T0 T1 T2 T2n T3 T3n
FIGURE 3 - EXTENDED MODE REGISTER DEFINITION
BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Address Bus
CLK CLK
COMMAND
READ
NOP CL = 2
NOP
NOP
01
11
Operating Mode
QFC# DS
DLL
Extended Mode Register (Ex)
DQS DQ
E0 0
DLL Enable Disable
T0
CLK CLK
T1
T2
T2n
T3
T3n
E1
1
Drive Strength Normal Reduced QFC# Function Disabled Reserved
COMMAND
READ
NOP
CL = 2.5
NOP
NOP
0 1 E22 0 -
DQS DQ
E12 E11 E10 E9 E8 0 E7 0 E6 0 E5 0 E4 0 E3 0 E2, E1, E0 Valid -
Operating Mode Reserved Reserved
Burst Length = 4 in the cases shown Shown with nominal tAC and nominal tDSDQ DATA
TRANSITIONING DATA DON'T CARE
0 -
0 -
0 -
0 -
1. E14 and E13 must be "0, 1" to select the Extended Mode Register (vs. the base Mode Register) 2. The QFE# function is not supported.
OUTPUT DRIVE STRENGTH
The normal full drive strength for all outputs are specified to be SSTL2, Class II. The DDR SDRAM supports an option for reduced drive. This option is intended for the support of the lighter load and/or point-to-point environments. The selection of the reduced drive strength will alter the DQs and DQSs from SSTL2, Class II drive strength to a reduced drive strength, which is approximately 54 percent of the SSTL2, Class II drive strength.
NO OPERATION (NOP)
The NO OPERATION (NOP) command is used to perform a NOP to the selected DDR SDRAM (CS# is LOW). This prevents unwanted commands from being registered during idle or wait states. Operations already in progress are not affected.
LOAD MODE REGISTER
The Mode Registers are loaded via inputs A0-12. The LOAD MODE REGISTER command can only be issued when all banks are idle, and a subsequent executable command cannot be issued until tMRD is met.
DLL ENABLE/DISABLE
The DLL must be enabled for normal operation. DLL enable is required during power-up initialization and upon returning to normal operation after having disabled the DLL for the purpose of debug or evaluation. (When the device exits self refresh mode, the DLL is enabled automatically.) Any time the DLL is enabled, 200 clock cycles must occur before a READ command can be issued.
ACTIVE
The ACTIVE command is used to open (or activate) a row in a particular bank for a subsequent access. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0-12 selects the row. This row remains active (or open) for accesses until a PRECHARGE command is issued to that bank. A PRECHARGE command must be issued before opening a different row in the same bank.
COMMANDS
The Truth Table provides a quick reference of available commands. This is followed by a written description of each command.
DESELECT
The DESELECT function (CS# HiGH) prevents new commands from being executed by the DDR SDRAM. The SDRAM is effectively deselected. Operations already in progress are not affected.
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TRUTH TABLE - COMMANDS (NOTE 1)
NAME (FUNCTION) DESELECT (NOP)(9) NO OPERATION (NOP) (9) ACTIVE (Select bank and activate row) (3) READ (Select bank and column, and start READ burst) (4) WRITE (Select bank and column, and start WRITE burst) (4) BURST TERMINATE (8) PRECHARGE (Deactivate row in bank or banks) (5) AUTO REFRESH or SELF REFRESH (Enter self refresh mode) (6,7) LOAD MODE REGISTER (2) CS# H L L L L L L L L RAS# X H L H H H L L L CAS# X H H L L H H L L WE# X H H H L L L H L ADDR X X Bank/Row Bank/Col Bank/Col X Code X Op-Code
TRUTH TABLE - DM OPERATION
NAME (FUNCTION) WRITE ENABLE (10) WRITE INHIBIT (10)
NOTES: 1 . CKE is HIGH for all commands shown except SELF REFRESH. 2 . A0-12 define the op-code to be written to the selected Mode Register. BA0, BA1 select either the mode register (0, 0) or the extended mode register (1, 0). 3. A0-12 provide row address, and BA0, BA1 provide bank address. 4. A0-8 provide column address; A10 HIGH enables the auto precharge feature (non-persistent), while A10 LOW disables the auto precharge feature; BA0, BA1 provide bank address. 5. A10 LOW: BA0, BA1 determine the bank being precharged. A10 HIGH: All banks precharged and BA0, BA1 are "Don't Care."
DM L H
DQs Valid X
6 . This command is AUTO REFRESH if CKE is HIGH; SELF REFRESH if CKE is LOW. 7 . Internal refresh counter controls row addressing; all inputs and I/Os are "Don't Care" except for CKE. 8. Applies only to read bursts with auto precharge disabled; this command is undefined (and should not be used) for READ bursts with auto precharge enabled and for WRITE bursts. 9 . DESELECT and NOP are functionally interchangeable. 10. Used to mask write data; provided coincident with the corresponding data.
READ
The READ command is used to initiate a burst read access to an active row. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A09 selects the starting column location. The value on input A10 determines whether or not AUTO PRECHARGE is used. If AUTO PRECHARGE is selected, the row being accessed will be precharged at the end of the READ burst; if AUTO PRECHARGE is not selected, the row will remain open for subsequent accesses.
PRECHARGE
The PRECHARGE command is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be available for a subsequent row access a specified time (tRP) after the PRECHARGE command is issued. Except in the case of concurrent auto precharge, where a READ or WRITE command to a different bank is allowed as long as it does not interrupt the data transfer in the current bank and does not violate any other timing parameters. Input A10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs BA0, BA1 select the bank. Otherwise BA0, BA1 are treated as "Don't Care." Once a bank has been precharged, it is in the idle state and must be activated prior to any READ or WRITE commands being issued to that bank. A PRECHARGE command will be treated as a NOP if there is no open row in that bank (idle state), or if the previously open row is already in the process of precharging.
WRITE
The WRITE command is used to initiate a burst write access to an active row. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A09 selects the starting column location. The value on input A10 determines whether or not AUTO PRECHARGE is used. If AUTO PRECHARGE is selected, the row being accessed will be precharged at the end of the WRITE burst; if AUTO PRECHARGE is not selected, the row will remain open for subsequent accesses. Input data appearing on the D/Qs iswritten to the memory array subject to the DQM input logic level appearing coincident with the data. If a given DQM signal is registered LOW, the corresponding data will be written to memory; if the DQM signal is registered HIGH, the corresponding data inputs will be ignored, and a WRITE will not be executed to that byte/column location.
AS4DDR32M72PBG1 Rev. 0.1 06/09
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i PEM 2.4Gb 2.4Gb SDRAM-DDR Austin Semiconductor, Inc. AS4DDR32M72PBG1
AUTO PRECHARGE
AUTO PRECHARGE is a feature which performs the same individual-bank PRECHARGE function described above, but without requiring an explicit command. This is accomplished by using A10 to enable AUTO PRECHARGE in conjunction with a specific READ or WRITE command. A precharge of the bank/row that is addressed with the READ or WRITE command is automatically performed upon completion of the READ or WRITE burst. AUTO PRECHARGE is nonpersistent in that it is either enabled or disabled for each individual READ or WRITE command. The device supports concurrent auto precharge if the command to the other bank does not interrupt the data transfer to the current bank. AUTO PRECHARGE ensures that the precharge is initiated at the earliest valid stage within a burst. This "earliest valid stage" is determined as if an explicit precharge command was issued at the earliest possible time, without violating tRAS (MIN).The user must not issue another command to the same bank until the precharge time (tRP) is completed. This is determined as if an explicit PRECHARGE command was issued at the earliest possible time, without violating tRAS (MIN). Although not a JEDEC requirement, to provide for future functionality features, CKE must be active (High) during the AUTO REFRESH period. The AUTO REFRESH period begins when the AUTO REFRESH command is registered and ends tRFC later.
SELF REFRESH*
The SELF REFRESH command can be used to retain data in the DDR SDRAM, even if the rest of the system is powered down. When in the self refresh mode, the DDR SDRAM retains data without external clocking. The SELF REFRESH command is initiated like an AUTO REFRESH command except CKE is disabled (LOW). The DLL is automatically disabled upon entering SELF REFRESH and is automatically enabled upon exiting SELF REFRESH (200 clock cycles must then occur before a READ command can be issued). Input signals except CKE are "Don't Care" during SELF REFRESH. The procedure for exiting self refresh requires a sequence of commands. First, CLK must be stable prior to CKE going back HIGH. Once CKE is HIGH, the DDR SDRAM must have NOP commands issued for tXSNR, because time is required for the completion of any internal refresh in progress. A simple algorithm for meeting both refresh and DLL requirements is to apply NOPs for 200 clock cycles before applying any other command.
* Self refresh available in commercial and industrial temperatures only.
BURST TERMINATE
The BURST TERMINATE command is used to truncate READ bursts (with auto precharge disabled). The most recently registered READ command prior to the BURST TERMINATE command will be truncated. The open page which the READ burst was terminated from remains open.
AUTO REFRESH
AUTO REFRESH is used during normal operation of the DDR SDRAM and is analogous to CAS#-BEFORE-RAS# (CBR) REFRESH in conventional DRAMs. This command is nonpersistent, so it must be issued each time a refresh is required. The addressing is generated by the internal refresh controller. This makes the address bits "Don't Care" during an AUTO REFRESH command. Each DDR SDRAM requires AUTO REFRESH cycles at an average interval of 7.8125s (maximum). To allow for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh interval is provided. A maximum of eight AUTO REFRESH commands can be posted to any given DDR SDRAM, meaning that the maximum absolute interval between any AUTO REFRESH command and the next AUTO REFRESH command is 9 x 7.8125s (70.3s). This maximum absolute interval is to allow future support for DLL updates internal to the DDR SDRAM to be restricted to AUTO REFRESH cycles, without allowing excessive drift in tAC between updates.
AS4DDR32M72PBG1 Rev. 0.1 06/09
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i PEM 2.4Gb 2.4Gb SDRAM-DDR Austin Semiconductor, Inc. AS4DDR32M72PBG1
ABSOLUTE MAXIMUM RATINGS
Parameter Voltage on VCC, VCCQ Supply relative to VSS Voltage on I/O pins relative to VSS Operating Temperature TA (Mil) Operating Temperature TA (Ind) Storage Temperature, Plastic -1 ot 3.6 -1 ot 3.6 -55 to +125 -40 to +85 -55 to +150 Unit V
o o o
V C C C
Note: Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in the operational conditions for extended periods may affect reliability.
CAPACITANCE (NOTE 13)
Parameter Input Capacitance: CLK Addresses, BA0-1 Input Capacitance Input Capacitance: All other input-only pins Input/Output Capacitance: I/O's Symbol C11 CA C12 C10 Max 8 30 9 12 Unit pF pF pF pF
AS4DDR32M72PBG1 Rev. 0.1 06/09
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i PEM 2.4Gb 2.4Gb SDRAM-DDR Austin Semiconductor, Inc. AS4DDR32M72PBG1
DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS (NOTES 1,6) VCC, VCCQ = +2.5V 0.2V; -55oC 0.2V, -55oC TA +125oC
Parameter / Condition Supply Voltage I/O Supply Voltage Input Leakage Current: Any input 0V VIN VCC (All other pins not under test = 0V) Symbol VCC VCCQ II II IOZ IOH IOL IOHR IOLR VREF VTT Min 2.3 2.3 -2 -10 -5 -12 12 -9 9 0.49 x VCCQ VREF - 0.04 Max 2.7 2.7 2 10 5 0.51 x VCCQ VREF + 0.04 Units V V A A A mA mA mA mA V V
Input Leakage Address Current (All other pins not under test = 0V) Output Leakage Current: I/O's are disabled; 0V VOUT VCC Output Levels: Full drive option High Current (VOUT = VCCQ - 0.373V, minimum VREF, minimum VTT) Low Current (VOUT = 0.373V, maximum VREF, maximum VTT) Output Levels: Reduced drive option High Current (VOUT = VCCQ - 0.763V, minimum VREF, minimum VTT) Low Current (VOUT = 0.763V, maximum VREF, maximum VTT) I/O Reference Voltage (6) I/O Termination Voltage (53)
AC INPUT OPERATING CONDITIONS (NOTES 1,6)14, 28, 40 VCC, VCCQ = +2.5V 0.2V; -55oC 0.2V, -55oC TA +125oC
Parameter / Condition Input High (Logic 1) Voltage: Input Low (Logic ) Voltage: Symbol Min VIH (AC) VREF + 0.310 VIL (AC) Max Units V VREF - 0.310 V
ICC SPECIFICATIONS AND CONDITIONS (NOTES 1-5, 10, 12, 14) VCC, VCCQ = +2.5V 0.2V; -55oC 0.2V, -55oC TA +125oC
Max Parameter / Condition OPERATING CURRENT: One bank, Active-Precharge; tRC = tRC (MIN); tCK = tCK (MIN); DQ, DM, and DQS inputs changing once per clock cycle; Address and control inputs changing once every two clock cycles; (22, 48) OPERATING CURRENT: One bank, Active-Read- Precharge; Burst=2; tRC = tRC (MIN); tCK = tCK (MIN); IOUT = 0mA; Address and control inputs changing once every two clock cycles; (22, 48) PRECHARGE POWER-DOWN STANDBY CURRENT: All banks idle; Power-down mode; tCK=tCK (MIN); CKE=LOW; (23, 32. 50) IDLE STANDBY CURRENT: CS#=HIGH, All banks idle; tCK=tCK (MIN); CKE=HIGH; Address and other control inputs changing once per clock cycle. VIN=VREF for DQ, DQS and DM (51) ACTIVE POWER-DOWN STANDBY CURRENT: One bank active; Power-down mode; tCK=tCK (MIN); CKE=LOW (23, 32, 50) ACTIVE STANDBY CURRENT: CS#=HIGH; CKE=HIGH; One bank; Active Precharge; tRC=tRAS (MAX); tCK=tCK (MIN); DQ, DM and DQS inputs changin twicer per clock cycle; Address and other control inputs changing once per clock cycle (22) OPERATING CURRENT: Burst=2; Reads; Continuous burst; One bank active; Address and control inputs changing once per clock cycle; tCK=tCK (MIN); IOUT=0mA (22,48) OPERATING CURRENT: Burst=2; Writes; Continuous burst; One bank active; Address and control inputs changing once per clock cycle; tCK=tCK (MIN); DQ, DM and DQS inputs changin twice per clock cycle (22) tREF=tRC (MIN) (27, 50) AUTO REFRESH CURRENT tREF=7.8125 s (27, 50) Standard (11) SELF REFRESH CURRENT: CKE 0.2V OPERATING CURRENT: Four bank interleaving DEADs (BL=4) with auto precharge, tRC=tRC (MIN); tCK=tCK (MIN); Addresses and control inputs change only during Active READ or WRITE commands. (22, 49) 333, 266 Symbol 250 Mbps ICC0 ICC1 ICC2P ICC2F ICC3P ICC3N ICC4R ICC4W ICC5 ICC5A ICC6 ICC7 625 200 Mbps Units 600 mA
850 20 225 150 250 925 800 1225 30 20 2000
775 20 225 150 250 925 800 1225 30 20 2000
mA mA mA mA mA mA mA mA mA mA mA
AS4DDR32M72PBG1 Rev. 0.1 06/09
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i PEM 2.4Gb 2.4Gb SDRAM-DDR Austin Semiconductor, Inc. AS4DDR32M72PBG1
ELECTRICAL CHARACTERISTICS AND CHARACTERISTICS (NOTES 1-5, 14-17, 33)
Parameter Access window of DQs from CLK/CLK# CLK high-level width (30) CLK low-level width (30) Clock cycle time CL=2.5 (45, 52) CL=2 (45, 52)
RECOMMENDED
-6, 333 [266] Mbps @CL=2.5 [CL=2] Min Max -0.70 +0.70 0.45 0.55 0.45 0.55 6 13 7.5 13 0.45 0.45 1.75 -0.6 +0.6 0.35 0.35 0.45 0.75 1.25 0.2 0.2 tCH, tCL +0.7 -0.7 0.75 0.75 0.8 0.8 12 tHP-tQHS 0.55 42 70,000 15 60 72 15 15 0.9 1.1 0.4 0.6 12 0.25 0 0.4 0.6 15 1 tQH - tDQSQ 70.3 35 7.8 3.9 0 75 200
AC
OPERATING
DQ and DM input hold time relative to DQS (26, 31) DQ and DM input setup time relative to DQS (26,31) DQ and DM input pulse with (for each input) (31) Access window of DQS from CLK/CLK# DQS input high pulse width DQS input high pulse width DQS-DQ skew, DQS to last valid, per group, per access (25,26) Write command to first DQS latching transition DQS falling edge to CLK rising - setup time DQS falling edge to CLK rising - hold time Half clock period (34) Data-out high-impedance window from CLK/CLK# (18, 42) Data-out low-impedance window from CLK/CLK# (18, 43) Address and control input hold time (fast slew rate) (14) Address and control input setup time (fast slew rate) (14) Address and control input hold time (slow slew rate) (14) Address and control input setup time (slow slew rate) (14) LOAD MODE REGISTER command cycle time DQ-DQS hold, DQS to first DQ to go non-valid, per access (25, 26) Data hold skew factor ACTIVE to PRECHARGE command (35) ACTIVE to READ with Auto precharge command ACTIVE to ACTIVE/AUTO REFRESH command period AUTO REFRESH command period (50) ACTIVE to READ or WRITE delay PRECHARGE command period DQS read preamble (42) DQS read postamble Active bank a to ACTIVE bank b command DQS write preamble DQS write preamble setup time (20,21) DQS write postamble (19) Write recovery time Internal WRITE to READ command delay Data valid output window (25) REFRESH to REFRESH command interval (Commercial & Industrial temp REFRESH to REFRESH command interval (Military temp only) (23) Average periodic refresh interval (Commercial & Industrial temp only) (23) Average periodic refresh interval (Military temp only) (23) Terminating voltage delay to Vcc (53) Exit SELF REFRESH to non-READ command Exit SELF REFRESH to READ command
AS4DDR32M72PBG1 Rev. 0.1 06/09
Symbol tAC tCH tCL tCK (2.5) tCK (2) tDH tDS tDIPW tDQSCK
tDQSH
tDQSL tDQSQ tDQSS tDSS tDSH tHP tHZ tLZ tIHF tISF tIHS tISS tMRD tQH tQHS tRAS tRAP tRC tRFC tRCD tRP tRPRE tRPST tRRD tWPRE tWPRES tWPST tWR tWTR NA tREFC tREFC tREFI tREFI tVTD tXSNR tXSRD
-75, 266 [250] Mbps @CL=2.5 [CL=2] Min Max -0.75 +0.75 0.45 0.55 0.45 0.55 7.5 13 8 13 0.5 0.5 1.75 -0.75 +0.75 0.35 0.35 0.5 0.75 1.25 0.2 0.2 tCH, tCL +0.75 -0.75 0.9 0.9 1.0 1.0 15 tHP-tQHS 1 40 120,000 15 60 75 15 15 0.9 1.1 0.4 0.6 15 0.25 0 0.4 0.6 15 1 tQH - tDQSQ 70.3 35 7.8 3.9 0 75 200
Units ns tCK tCK ns ns ns ns ns ns tCK tCK ns tCK tCK tCK ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns tCK tCK ns tCK ns tCK ns tCK ns s s s s ns ns tCK
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i PEM 2.4Gb 2.4Gb SDRAM-DDR Austin Semiconductor, Inc. AS4DDR32M72PBG1
ELECTRICAL CHARACTERISTICS AND CHARACTERISTICS (NOTES 1-5, 14-17, 33)
Parameter Access window of DQs from CLK/CLK# CLK high-level width (30) CLK low-level width (30) Clock cycle time CL=2.5 (45, 52) CL=2 (45, 52)
RECOMMENDED
-8, 250 [200] Mbps @CL=2.5 [CL=2] Min Max -0.8 +0.8 0.45 0.55 0.45 0.55 8 13 10 13 0.6 0.6 2 -0.8 +0.8 0.35 0.35 0.6 0.75 1.25 0.2 0.2 tCH, tCL +0.8 -0.8 1.1 1.1 1.1 1.1 16 tHP-tQHS 1 40 120,000 20 70 80 20 20 0.9 1.1 0.4 0.6 15 0.25 0 0.4 0.6 15 1 tQH-tDQSQ 70.3 35 7.8 3.9 0 80 200
AC
OPERATING
DQ and DM input hold time relative to DQS (26, 31) DQ and DM input setup time relative to DQS (26,31) DQ and DM input pulse with (for each input) (31) Access window of DQS from CLK/CLK# DQS input high pulse width DQS input high pulse width DQS-DQ skew, DQS to last valid, per group, per access (25,26) Write command to first DQS latching transition DQS falling edge to CLK rising - setup time DQS falling edge to CLK rising - hold time Half clock period (34) Data-out high-impedance window from CLK/CLK# (18, 42) Data-out low-impedance window from CLK/CLK# (18, 43) Address and control input hold time (fast slew rate) (14) Address and control input setup time (fast slew rate) (14) Address and control input hold time (slow slew rate) (14) Address and control input setup time (slow slew rate) (14) LOAD MODE REGISTER command cycle time DQ-DQS hold, DQS to first DQ to go non-valid, per access (25, 26) Data hold skew factor ACTIVE to PRECHARGE command (35) ACTIVE to READ with Auto precharge command ACTIVE to ACTIVE/AUTO REFRESH command period AUTO REFRESH command period (50) ACTIVE to READ or WRITE delay PRECHARGE command period DQS read preamble (42) DQS read postamble Active bank a to ACTIVE bank b command DQS write preamble DQS write preamble setup time (20,21) DQS write postamble (19) Write recovery time Internal WRITE to READ command delay Data valid output window (25) REFRESH to REFRESH command interval (Commercial & Industrial temp REFRESH to REFRESH command interval (Military temp only) (23) Average periodic refresh interval (Commercial & Industrial temp only) (23) Average periodic refresh interval (Military temp only) (23) Terminating voltage delay to Vcc (53) Exit SELF REFRESH to non-READ command Exit SELF REFRESH to READ command
AS4DDR32M72PBG1 Rev. 0.1 06/09
Symbol tAC tCH tCL tCK (2.5) tCK (2) tDH tDS tDIPW tDQSCK
tDQSH
tDQSL tDQSQ tDQSS tDSS tDSH tHP tHZ tLZ tIHF tISF tIHS tISS tMRD tQH tQHS tRAS tRAP tRC tRFC tRCD tRP tRPRE tRPST tRRD tWPRE tWPRES tWPST tWR tWTR NA tREFC tREFC tREFI tREFI tVTD tXSNR tXSRD
-10, 200 [167] Mbps @CL=2.5 [CL=2] Min Max -0.8 +0.8 0.45 0.55 0.45 0.55 10 13 13 15 0.6 0.6 2 -0.8 +0.8 0.35 0.35 0.6 0.75 1.25 0.2 0.2 tCH, tCL +0.8 -0.8 1.1 1.1 1.1 1.1 16 tHP-tQHS 1 40 120,000 20 70 80 20 20 0.9 1.1 0.4 0.6 15 0.25 0 0.4 0.6 15 1 tQH-tDQSQ 70.3 35 7.8 3.9 0 80 200
Units ns tCK tCK ns ns ns ns ns ns tCK tCK ns tCK tCK tCK ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns tCK tCK ns tCK ns tCK ns tCK ns s s s s ns ns tCK
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i PEM 2.4Gb 2.4Gb SDRAM-DDR Austin Semiconductor, Inc. AS4DDR32M72PBG1
NOTES: 1. All voltages referenced to VSS. 2. Tests for AC timing, ICC, and electrical AC and DC characteristics may be conducted at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. 3. Outputs measured with equivalent load:
VTT
50 Output (VOUT) Reference Point 30pF
4. AC timing and ICC tests may use a VIL-to-VIH swing of up to 1.5V in the test environment, but input timing is still referenced to VREF (or to the crossing point for CLK/CLK#), and parameter specifications are guaranteed for the specified AC input levels under normal use conditions. The minimum slew rate for the input signals used to test the device is 1V/ns in the range between VIL(AC) and VIH(AC). 5. The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e., the receiver will effectively switch as a result of the signal crossing the AC input level, and will remain in that state as long as the signal does not ring back above [below] the DC input LOW [HIGH] level). 6. VREF is expected to equal VCCQ/2 of the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise (noncommon mode) on VREF may not exceed 2 percent of the DC value. Thus, from VCCQ/2, VREF is allowed 25mV for DC error and an additional 25mV for AC noise. This measurement is to be taken at the nearest VREF by-pass capacitor. 7. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF and must track variations in the DC level of VREF. 8. VID is the magnitude of the difference between the input level on CLK and the input level on CLK#. 9. The value of VIX and VMP are expected to equal VCCQ/2 of the transmitting device and must track variations in the DC level of the same. 10. ICC is dependent on output loading and cycle rates. Specified values are obtained with minimum cycle time with the outputs open.
15. The CLK/CLK# input reference level (for timing referenced to CLK/CLK#) is the point at which CLK and CLK# cross; the input reference level for signals other than CLK/CLK# is VREF. 16. Inputs are not recognized as valid until VREF stabilizes. Exception: during the period before VREF stablizes, CKE < 0.3 x VCCQ is recognized as LOW. 17. The output timing reference level, as measured at the timing reference point indicated in Note 3, is VTT. 18. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referenced to a specific voltage level, but specify when the device output is no longer driving (HZ) or begins driving (LZ). 19. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this parameter, but system performance (bus turnaround) will degrade accordingly. 20. This is not a device limit. The device will operate with a negative value, but system performance could be degraded due to bus turnaround. 21. It is recommended that DQS be valid (HIGH or LOW) on or before the WRITE command. The case shown (DQS going from High-Z to logic LOW) applies when no WRITEs were previously in progress on the bus. If a previous WRITE was in progress, DQS could be HIGH during this time, depending on tDQSS. 22. MIN (tRC or tRFC) for ICC measurements is the smallest multiple of tCK that meets the minimum absolute value for the respective parameter. tRAS (MAX) for ICC measurements is the largest multiple of tCK that meets the maximum absolute value for tRAS. 23. The refresh period 64ms. This equates to an average refresh rate of However, an AUTO REFRESH command must be asserted at least once every 70.3s; burst refreshing or posting by the DRAM controller greater than eight refresh cycles is not allowed. The I/O capacitance per DQS and DQ byte/group will not differ by more than this maximum amount for any given device. The valid data window is derived by achieving other specifications - tHP (tCK/2), tDQSQ, and tQH (tQH = tHP - tQHS). The data valid window derates directly porportional with the clock duty cycle and a practical data valid window can be derived. The clock is allowed a maximum duty cycle variation of 45/55. Functionality is uncertain when operating beyond a 45/55 ratio. The data valid window derating curves are provided Referenced to each output group: LDQS with DQ0-DQ7; and UDQS with DQ8-DQ15 of each chip. This limit is actually a nominal value and does not result in a fail value. CKE is HIGH below for duty cycles ranging between 50/50 and 45/55. during REFRESH command period (tRFC [MIN]) else CKE is LOW (i.e., during standby) To maintain a valid level, the transitioning edge of the input must: a) Sustain a constant slew rate from the current AC level through to the target AC level, VIL(AC) or VIH(AC). b) Reach at least the target AC level. c) After the AC target level is reached, continue to maintain at least the target DC level, VIL(DC) or VIH(DC).
24. 25.
26. 27.
11. Enables on-chip refresh and address counters. 12. ICC specifications are tested after the device is properly initialized, and is 28. averaged at the defined cycle rate. 13. This parameter is not tested but guaranteed by design. tA = 25OC, f = 1 MHz 14. Command/Address input slew rate = 0.5V/ns. For 266 MHz with slew rates 1V/ns and faster, tIS and tIH are reduced to 900ps. If the slew rate is less than 0.5V/ns, timing must be derated: tIS has an additional 50ps per each 100mV/ns reduction in slew rate from the 500mV/ns. tIH has 0ps added, that is, it remains constant. If the level, slew rate exceeds 4.5V/ns, functionality is uncertain.
FIGURE A - PULL-DOWN CHARACTERISTICS
160
FIGURE B - PULL-UP CHARACTERISTICS
0 -20 -40
140
Maximum
Minimum Nominal low
120
Nominal high
100
-60 -80 -100 -120 -140 -160
IOUT (mA)
80
Nominal low
60
IOUT (mA)
Nominal high
Minimum
40
20
-180 -200 0.0 0.5 1.0 1.5 2.0 2.5 0.0 0.5 1.0 1.5 2.0
Maximum
0
2.5
VOUT (V)
VCCQ - VOUT (V)
AS4DDR32M72PBG1 Rev. 0.1 06/09
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i PEM 2.4Gb 2.4Gb SDRAM-DDR Austin Semiconductor, Inc. AS4DDR32M72PBG1
29. The Input capacitance per pin group will not differ by more than this maximum amount for any given device. 30. CLK and CLK# input slew rate must be > 1V/ns (>2V/ns differentially). 31. DQ and DM input slew rates must not deviate from DQS by more than 10%. If the DQ/DM/DQS slew rate is less than 0.5V/ns, timing must be derated: 50ps must be added to tDS and tDH for each 100mV/ns reduction in slew rate. If slew rate exceeds 4V/ns, functionality is uncertain. 32. VCC must not vary more than 4% if CKE is not active while any bank is active. 33. The clock is allowed up to 150ps of jitter. Each timing parameter is allowed to vary by the same amount. 34. tHP min is the lesser of tCL minimum and tCH minimum actually applied to the device CLK and CLK# inputs, collectively during bank active. 35. READs and WRITEs with auto precharge are not allowed to be issued until tRAS(MIN) can be satisfied prior to the internal precharge command being issued. 36. Any positive glitch must be less than 1/3 of the clock and not more than +400mV or 2.9 volts, whichever is less. Any negative glitch must be less than 1/3 of the clock cycle and not exceed either -300mV or 2.2 volts, whichever is more positive. 37. Normal Output Drive Curves: a) The full variation in driver pull-down current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the V-I curve of Figure A. b) The variation in driver pull-down current within nominal limits of voltage and temperature is expected, but not guaranteed, to lie within the inner bounding lines of the V-I curve of Figure A. c) The full variation in driver pull-up current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the V-I curve of Figure B. d) The variation in driver pull-up current within nominal limits of voltage and temperature is expected, but not guaranteed, to lie within the inner bounding lines of the V-I curve of Figure B. e) The full variation in the ratio of the maximum to minimum pull-up and pull-down current should be between .71 and 1.4, for device drainto-source voltages from 0.1V to 1.0 Volt, and at the same voltage and temperature. f) The full variation in the ratio of the nominal pull-up to pull-down current should be unity A10%, for device drain-to-source voltages from 0.1V to 1.0 Volt. 38. Reduced Output Drive Curves: a) The full variation in driver pull-down current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the V-I curve of Figure C. b) The variation in driver pull-down current within nominal limits of voltage and temperature is expected, but not guaranteed, to lie within the inner bounding lines of the V-I curve of Figure C. c) The full variation in driver pull-up current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the V-I curve of Figure D. d) The variation in driver pull-up current within nominal limits of voltage and temperature is expected, but not guaranteed, to lie within the inner bounding lines of the V-I curve of Figure B. e) The full variation in the ratio of the maximum to minimum pull-up and pull-down current should be between .71 and 1.4, for device drainto-source voltages from 0.1V to 1.0 Volt, and at the same voltage and temperature. f) The full variation in the ratio of the nominal pull-up to pull-down current should be unity 10%, for device drain-to-source voltages from 0.1V to 1.0 Volt. The voltage levels used are derived from a minimum VCC level and the referenced test load. In practice, the voltage levels obtained from a properly terminated bus will provide significantly different voltage values. VIH overshoot: VIH(MAX) = VCCQ+1.5V for a pulse width < 3ns and the pulse width can not be greater than 1/3 of the cycle rate. VCC and VCCQ must track each other. This maximum value is derived from the referenced test load. In practice, the values obtained in a typical terminated design may reflect up to 310ps less for tHZ(MAX) and the last DVW. tHZ(MAX) will prevail over tDQSCK(MAX) + tRPST(MAX) condition. tLZ(MIN) will prevail over tDQSCK(MIN) + tRPRE(MAX) condition. For slew rates greater than 1V/ns the (LZ) transition will start about 310ps earlier. During initialization, VCCQ, VTT, and VREF must be equal to or less than VCC + 0.3V. Alternatively, VTT may be 1.35V maximum during power up, even if VCC/VCCQ are 0 volts, provided a minimum of 42 ohms of series resistance is used between the VTT supply and the input pin. The current part operates below the slowest JEDEC operating frequency of 83 MHz. As such, future die may not reflect this option. Reserved for future use. Reserved for future use. Random addressing changing 50% of data changing at every transfer. Random addressing changing 100% of data changing at every transfer. CKE must be active (high) during the entire time a refresh command is executed. That is, from the time the AUTO REFRESH command is registered, CKE must be active at each rising clock edge, until tRFC has been satisfied. ICC2N specifies the DQ, DQS, and DM to be driven to a valid high or low logic level. ICC2Q is similar to ICC2F except ICC2Q specifies the address and control inputs to remain stable. Although ICC2F, ICC2N, and ICC2Q are similar, ICC2F is "worst case." Whenever the operating frequency is altered, not including jitter, the DLL is required to be reset. This is followed by 200 clock cycles before any READ command. VTT is not applied directly to the device; however, tVTD should be greater than or equal to zero to avoid device latch-up. VCCQ, VTT and VREF must be equal to or less than VCC + 0.3V. Alternatively VTT may be 1.35V max during power-up even if VCC/VCCQ are 0V, provided a minimum of 42 &! of series resistance is used between the VTT supply and the input pin. Once initialized, VREF must always be powered within the specified range.
39. 40. 41. 42.
43. 44.
45. 46. 47. 48. 49. 50.
51.
52. 53.
FIGURE C - PULL-DOWN CHARACTERISTICS
80
FIGURE D - PULL-UP CHARACTERISTICS
0 -10
Maximum
70
60
Nominal high
-20
Minimum
50
-30
Nominal low
IOUT (mA)
IOUT (mA)
40
Nominal low
-40
30
-50
Minimum
20 -60
Nominal high
10
-70
Maximum
0 0.0 0.5 1.0 1.5 2.0 2.5 -80 0.0 0.5 1.0 1.5 2.0 2.5
VOUT (V)
VCCQ - VOUT (V)
AS4DDR32M72PBG1 Rev. 0.1 06/09
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
15
i PEM 2.4Gb 2.4Gb SDRAM-DDR Austin Semiconductor, Inc. AS4DDR32M72PBG1
MECHANICAL DIAGRAM
208 x O 0.60 (0.024) NOM 11 10 9 8 7 6 5 4 3 2 1
A B C D E F G
24.15 (0.951) MAX
18.0 (0.709) NOM
H J K L 2.
1.0 (0.039) NOM
M N P R T U V W
1.0 (0.039)NOM 0.50 (0.020) NOM 10.0 (0.394) NOM
16.15 (0.636) MAX
2.00 (0.079) MAX
AS4DDR32M72PBG1 Rev. 0.1 06/09
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
16
i PEM 2.4Gb 2.4Gb SDRAM-DDR Austin Semiconductor, Inc. AS4DDR32M72PBG1
ORDERING INFORMATION
Part Number AS4DDR32M72PBG1-6/IT AS4DDR32M72PBG1-75/IT AS4DDR32M72PBG1-8/IT AS4DDR32M72PBG1-10/IT AS4DDR32M72PBG1-6/ET AS4DDR32M72PBG1-75/ET AS4DDR32M72PBG1-8/ET AS4DDR32M72PBG1-10/ET AS4DDR32M72PBG1-6/XT AS4DDR32M72PBG1-75/XT AS4DDR32M72PBG1-8/XT AS4DDR32M72PBG1-10/XT
Core Freq. Data Transfer Rate 166 MHz 333 Mbps 133 MHz 266 Mbps 125 MHz 250 Mbps 100 MHz 200 Mbps 166 MHZ 133 MHz 125 MHz 100 MHz 166 MHZ 133 MHz 125 MHz 100 MHz 333 Mbps 266 Mbps 250 Mbps 200 Mbps 333 Mbps 266 Mbps 250 Mbps 200 Mbps
Package Process 208-PBGA Industrial 208-PBGA Industrial 208-PBGA Industrial 208-PBGA Industrial 208-PBGA 208-PBGA 208-PBGA 208-PBGA 208-PBGA 208-PBGA 208-PBGA 208-PBGA Enhanced Enhanced Enhanced Enhanced Extended Extended Extended Extended
AS4DDR32M72PBG1 Rev. 0.1 06/09
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
17
i PEM 2.4Gb 2.4Gb SDRAM-DDR Austin Semiconductor, Inc. AS4DDR32M72PBG1
DOCUMENT TITLE 32M x 72 DDR SDRAM Multi-Chip Packaged in a 32mm x 25mm - 208 PBGA REVISION HISTORY Rev # 0.0 0.1 History INITIAL RELEASE Updated Order Chart Changed "Extended" to "Military" Temp Release Date September 2008 June 2008 Status Advance Advance
AS4DDR32M72PBG1 Rev. 0.1 06/09
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
18

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